1. Field
The embodiments discussed herein are related to a semiconductor storage device and control methods thereof.
2. Description of the Relate Art
FIG. 1 illustrates a conventional semiconductor storage device. A semiconductor storage device 1 includes a multistage buffer 10, clock control circuits 20-1 to 20-n, an address decoding circuit 30 which selects a buffer used for writing and an address decoding circuit 40 which selects a buffer used for reading. The multistage buffer 10 is an n-stage buffer (n is a natural number equal to or greater than 2) including buffers 11-1 to 11-n. Each of the buffers 11-1 to 11-n include an m-stage flip-flop (m is a natural number) including flip-flops 12-0 to 12 (m−1). FIG. 1 illustrates, input data 130 to be written to the multistage buffer 10, ODT represents output data to be read from the multistage buffer 10, an address signal 120, and a clock signal 100.
A clock signal 100 is supplied only to a buffer corresponding to a selected address from a corresponding one of the clock signal circuits 20-1 to 20-n. Thus, it is possible to operate only a single buffer among the multistage buffer 10. Since no clock signals 100 are supplied to buffers other than the buffer corresponding to the selected address, power consumption of the entire semiconductor storage device 1 can be reduced.
However, an increase in the number of stages n of the multistage buffer 10 leads to an increase in the mounting area of the semiconductor storage device 1 and thus an increase in the data transmission distance. Therefore, it is desired to amplify data by providing transfer buffers in signal lines which transfer data. Since such transfer buffers are provided at designated intervals and at each stage of the multistage buffer 10, an increase in the number of stages n of the multistage buffer 10 results in a significant number of transfer buffers. While FIG. 1 illustrates only some transfer buffers as transfer buffers 15, the actual number of the transfer buffers 15 may vary, e.g., be large.
Therefore, even if an attempt is made to reduce the power consumption of the entire semiconductor storage device 1 by supplying a clock signal 100 only to a buffer in the multistage buffer 10 which corresponds to a selected address, the individual transfer buffers 15 keep operating, and thus the amount of reduction of power consumption may be limited.